The present invention relates to a biphase shift keying modulation circuit, and more particularly to a circuit for converting random digital data into an in-phase signal component and quadrature phase signal component which are modulated respectively at carrier waves of 90.degree. different phases and added to each other so as to provide a signal of flat envelope characteristics.
FIG. 1 shows a conventional circuit, wherein a data generating unit 200 divides the frequency of the system clock pulses "a" through a system clock input terminal 100 so as to provide random data in synchronism with the system clock pulses. The frequency-divided random data from the data generating unit 200 is synchronized with the system clock pulses "a" by a data conversion circuit 300 to produce stepped in-phase and quadrature phase signal components. A carrier wave generator 170 generates a carrier wave. A modulator circuit 400 modulates the in-phase and quadrature phase signal components of the data conversion circuit 300 respectively at a carrier wave and the carrier wave shifted by 90.degree. into double and single balanced signals that are combined so as to generate a signal of flat envelope characteristics. The modulated signal from the modulator circuit 400 is amplified by an amplifier 220 to class C. The amplified signal from the amplifier 220 is transmitted through an antenna ANT.
The data generating unit 200 has a frequency divider 110 for dividing the frequency of the system clock pulses "a" by a given frequency division rate, and a random data generator 120 for receiving the output of the frequency divider 110 to provide random digital data "c".
A data conversion circuit 300 has a shift register 130, a first resistor array 140, a gate array 150, and a second resistor array 160. The shift register 130 receives the frequency-divided signal from the data generator 120 in series and delays the signal at a given number of times by a given period, in order to simultaneously produce all the delayed signals in parallel. The parallel signals D0-D7 from the shift register 130 are respectively multiplied by a given value of the first resistor array 140 and added to each other, to provide an in-phase signal component "l". In addition, assuming that one of the parallel signals from the shift register 130 is Dj, Dj and D(N-j+1)(N is the number of the parallel signal outputs from the shift register 130, and j =1, 2, . . . , N/2) are XORed via the gate array 150 of exclusive-OR gates. The signals from the gate array 150 are respectively multiplied by given values of a second resistor array 160 and added to each other, to provide a quadrature phase signal component "q".
The modulation circuit 400 has a carrier wave generator 170 for generating a carrier wave, a first multiplier 180 for multiplying the in-phase signal component with the carrier from the carrier wave generator 70 to perform a double balanced modulation, a phase shifter 190 for shifting the carrier from the carrier wave generator 170 by 90.degree., a second multiplier 230 for multiplying the quadrature phase signal component with the phase-shifted carrier from the phase shifter 190 to perform a single balanced modulation balanced only for the quadrature phase signal component, and an adder 210 for adding the signal from the first multiplier 180 to the signal from the second multiplier 230. The first and second resistor arrays 140 and 160 have a plurality of resistors R1-R14, and the gate array 150 has a plurality of XOR gates G1-G4. This prior art is disclosed in a Korea Patent Application No. 90-15940.
The waveforms of the parts of FIG. 1 are shown in FIG. 2, wherein waveform "a" illustrates the system clock pulses, waveform "b" the system clock pulses divided by the frequency divider 110, waveform "c" the signal from the random data generator 120, waveforms "d" and "k" the random data shifted by the shift register 130 in synchronism with the system clock pulses "a", waveform "l" the in-phase data obtained by multiplying the waveforms "d" to "k" from the shift register 130 through the first resistor array 140 by given values and adding the multiplied waveforms, waveform "m" the signal obtained by XORing the waveforms "d" and "k" via a XOR gate, waveform "n" the signal obtained by XORing the waveforms "e" and "j" via XOR gates, waveform "o" the signal obtained by XORing the waveforms "f" and "i" via XOR gates, waveform "p" the signal obtained by XORing the waveforms "g" and "h" via XOR gates, waveform "q" quadrature phase data obtained by multiplying the waveforms "m" and "p" from the gate array 150 through the second resistor array 160 by given values and adding the multiplied waveforms, waveform "r" the signal obtained by multiplying the waveform "l" at the carrier wave, waveform "s" the signal obtained by multiplying the waveform "q" with the carrier signal shifted 90.degree., and waveform "t" the modulated signal obtained by adding the waveform "r" to the waveform "s".
The operation of the conventional circuit is illustrated hereinafter. The frequency divider 110 divides the frequency of the system clock pulses "a" through the input terminal 100 by a given frequency division rate as shown in waveform "b" of FIG. 2. The waveform "b" from the frequency divider 110 is applied to the random data generator 120 to generate random digital data as shown in waveform "c" of FIG. 2. Meanwhile, the shift register 130 of the data conversion circuit 300 receives the waveform "c" from the random data generator 120 through an input terminal Di and shifts the waveform "c" according to the system clock pulses "a", to generate signals as shown in waveforms "d" to "k" of FIG. 2 through output terminals D0 to D7. In this case, the signal from the terminal D0 is obtained by once delaying the signal "c". Likewise, the signal from the terminal D2 is obtained by once delaying the signal from the terminal D1. In this way, the signal from the terminals D3 to D7 are respectively obtained by sequentially delaying the signals from the terminals D0 and D2. As a result, the signal from the terminal D7 is obtained by eight times delaying the waveform "c" from the random data generator 120. The output timing of the output terminals D0 to D7 is synchronized with the system clock pulses "a" so as to simultaneously generate the signals. The first resistor array 140 multiplies the signals from the shift register 130 respectively by the resistors R1-R9 , and adds the multiplied signals to provide the in-phase signal component shown as waveform "l" of FIG. 2. The gate array 150 XORs the signals from the output terminal Dj of the shift register 130, i.e., XORs the signals from the output terminals D(N-j+1)(N is the number of the parallel output terminals, j=1, 2, . . . , N/2) and Dj via the XOR gates G1-G4. The signals from the gate array 150 are respectively multiplied by the resistors R10 to R13, and the multiplied signals are added to each other to provide the quadrature phase signal component as shown in waveform "q" of FIG. 2.
Assuming that the in-phase and quadrature phase signal components are functions of time labeled respectively I(t) and Q(t), a modulated signal should satisfy the relationship [I(t)].sup.2 +[Q(t)].sup.2 =C (C is a constant) in order to have flat envelope characteristics. The resistances of the first and second resistor arrays 140 and 160 may be respectively determined so as to maintain the relationship.
The carrier wave generator 170 generates the carrier wave that is multiplied by the waveform "l" from the first resistor array 140 in double balanced modulation via the first multiplier 180 of the modulator circuit 400 to produce a signal as shown in waveform "r" of FIG. 2. Further, the second multiplier 230 multiplies the signal from the phase shifter 190 and the waveform "q" from the second resistor array in single balanced modulation to produce a signal as shown in waveform "s" of FIG. 2. The adder 210 adds the waveform "r" from the first multiplier 180 to waveform "s" from the second multiplier 230 to produce the biphase shift keying modulated signal with flat envelope characteristics as shown in waveform "t" of FIG. 2, which biphase shift keying signal may be sufficiently amplified even in class C so as to be transmitted through the antenna ANT to the receiver.
However, since the second multiplier 230 is a single balanced modulator that is balanced for the carrier wave but not for the data, receiving the data with a direct current component as shown in the waveform "q" of FIG. 2 produces a signal with the carrier frequency component and harmonic component therearound, which is analyzed by a spectrum analyzer to show the spikes as shown in FIG. 3A. This may cause energy loss and impair other frequency regions in data transmission.